The present invention generally relates to semiconductor integrated circuits and methods for making wiring layouts of semiconductor integrated circuits. More particularly, the present invention relates to a semiconductor integrated circuit, in which input/output cell regions are provided around an inner cell region and pads are provided between the input/output cell regions and the sides of the semiconductor integrated circuit, and a method for making a wiring layout of such a semiconductor integrated circuit.
FIG. 1 is a schematic diagram showing a plan view of an embodiment of a conventional semiconductor integrated circuit (hereinafter also referred to as SIC). As shown in FIG. 1, the SIC is comprised of a semiconductor chip (element) 1, a plurality of pads 2, a plurality of input/output cell regions 3 (hereinafter also referred to as I/O cell regions 3), and an inner cell region 4.
In the SIC shown in FIG. 1, the plurality of I/O cell regions 3, each I/O cell region 3 having an identical size, are provided around the inner cell region 4. Also, each I/O cell is formed by one or more of the I/O cell regions 3.
However, there is a need for various types of I/O cells in terms of function and, in the conventional SIC shown in FIG. 1, a problem exists in that the area required for a particular I/O cell does not always match the area formed by one or more of the I/O cell regions 3. Therefore, an area larger than the required area is usually used for an individual I/O cell, and hence the surface of the semiconductor chip 1 is not used efficiently nor effectively.
Also, in the conventional SIC shown in FIG. 1, a wiring layout is performed by using an I/O cell having a wiring pattern which is not necessary for itself but necessary for other I/O cells.
However, it is not easy to carry out such a layout method, and not much flexibility is available in the method.